Technical Program 2024

TECHNICAL TRACKS & TITLES

 

Artificial Intelligence 

• Zeroing in on Quality – A Deep Learning Ensembled Approach to Ensure Socket Manufacturing Line Quality
• A Comprehensive System for Machine Learning and End-to-End ModelOps at the Edge
• Using RITdb and ACS Real-Time Data Infrastructure to Enable Analytics
• Improving Efficiency and Robustness of Gaussian Process Based Outlier Detection via Ensemble Learning
• Smart Classification through Artificial Intelligence for Time Domain Reflectometry

 

5G/Millimeter Wave  

• Best Test Practices with V93000 for 5G RRU Transceiver with Ultra-Low NF
• Merging Two Tester Platforms: Integrating ROOS mmWave System with the V93000 for mmWave Testing
• Practical OTA Test Challenges for 5G NR mmWave AiP on V93000 WSMM
• A Practice for Testing a Wi-Fi 7 Transceiver with 320MHz Bandwidth
• 5G mmWave Port-to-Port Phase Difference Measurement and Compensation Correlated to VNA Using WaveScale Millimeter
• mmWave testing on WSMM: Tips and Tricks
• An Extreme Low Phase Noise On-board Measurement Solution for PLL Devices Up to 19.6GHz
• Digital Pre-Distortion for RF Power Amplifiers on V93000
• Demodulation of WiFi Signals without a Header
• Test Time Optimization for Wi-Fi Product Validation Using New V93000 EXA Scale SoC Test System
• A Real Case to Reduce COT and Improve TTV for 5G Transceiver Application
• Comparing Different EVM Measurement Methods and Their Value for Different Wi-Fi Applications
• Overcoming MIPI Interface Challenges in Radar Applications on ATE Test Platforms

 

High Performance Digital 

• Evaluation of a MEMS Switch to Support PCIe Gen 6 External Loopback Test and PCIe Protocol-Based Scan Test
• High-Speed Performance Testing Strategy and Solution for AI Wave
• Mux/Demux On-Board Solution for Scan-Over-HSIO with 10Gbps or Higher
• HSIO Scan Test Implemented in a Real Case with PS5000 on V93000 EXA Scale
• An Optimized Test Solution for 128-Core CPU on V93000 EXA Scale Platform
• Pulse Width Modulation High-Speed Interface Characterization to Production Utilizing V93000 High-Speed Digital Instrumentation with Real-Time Sampling
• Display Port Test Implementation using Pin Scale Multilevel Serial
• PAM4 Signaling with Pin Scale Multilevel Serial
• Test Content-Aware Native Power Profiling Accelerates Product Bring-up and Helps Monitor Test Cell Health in Production
• High-Performance Signal Generation of MIPI D-PHY via V93000 EXA Scale Platform
• PS5000 High-Current Evaluation
• Successful Migration to a new EXA Scale high-density high-current power supply for testing of HPC/Mobile/AI devices

 

Parametric Test

• Universal Web-Based Program Generator for Parametric Test
• API for Offline Algorithm Debug in PT Software
• Setting Checkpoints and Time Savings in Asynchronous Testing
• Safe AVI64 Connect/Disconnect with Parametric Test System
• Analyzing Test-Structure Capacitance and Resistivity for Reliable Capacitance Measurements

 

Hardware & Software Design Integration

• High-Current Test Evaluation and Solution for Door Devices
• Innovative Automated Massive Test Table Setup for Complex AI Chip Testing
• Protocol Link: a MIPs Empowered Hardware Protocol Solution on V93000 EXA Scale
• Generic V93000 Correlation Tool Accelerates EXA Scale Migration
• Generating V93000 Test Programs from Advanced Spreadsheet-Based Tabular EDA Data and Patterns
• An Accelerating ADAS ATE Development Solution in EXA Scale EX
• Novel Solution for Wi-Fi 7 RF and HSIO Path Loss Measurement Efficiency up to Pogo Pins Level
• SOCtml Component Library
• Using a RESTful Web Service to Control the V93000: Integration of an ATE into an Engineering Environment to Improve TTM
• Exalib: A Flexible Test Program Library for EXA Scale and SmarTest 8

 

Test Methodologies

• Highly Multisite Front-End Test Solution Design and Implementation for Automotive Testing
• A Generic Solution to Handle System in Package Fuse Test in Multiple Flows
• Boost Test Program Development Performance through Burst and Concurrency on SmarTest 8
• Test Program Migration from SmarTest 7 to SmarTest 8
• Asynchronous Clock Communication Test Based on Digital Audio Interface
• Automated High-Speed Digital and High-Performance RF Testing in Volume Manufacturing Using a Modified Flying Probe Tester
• Best Practice of TTR and TTM Improvement on a 5G Transceiver with High-Speed DigRF Interface
• SOC-RF 16 Site Solution on V93000 EXA Platform with DUO Interface
• Innovative Methodology to Overcome Challenges in Generating Waveform Per Site in AVI64
• Best Practice of SmarTest 8 Library Transition for AI and HPC Applications
• Best Practice of SmarTest 8 in POD Characterization Test for High-Volume GPU Devices
• An Effective Access and Test Solution for Stacked-Die Devices on V93000
• Methodologies in SmarTest 8 to Ease Chiplet Testing
• Trim Down Your Trim Test Development: A Trimming Framework for SmarTest 8
• Algorithmic Test Time Reduction on SmarTest 8
• Capturing Wi-Fi 7 LO Frequency Transition Time with WaveScale RF8
• Low-Cost HVM Solution for High-Pin-Count Source-Driver IC on T6391
• Die-Level Test (DLT): A New Production Solution for Final Test at the Die Level
• A Highly Efficient Test Method for Running Tessent SSN Test and On-Chip Compare in One Test Suite on the V93000 Platform
• Test Time Optimization Techniques for ADC Performance Measurements
• Introduction of Real Customer Analog Application Cases on WaveScale MX on SmarTest 7.10
• Enabling Virtual Scope capability on the V93000
• Development of SmarTest 8 SSN Single Test Method Handling On-chip and On-Tester Compare Addressing Production and Characterization Use Cases
• Introducing a New Cost-Effective Methodology to Measure Low-pF Capacitance for Massive Multisite Applications
• Improving EVM Results of Wi-Fi 7 Signals Using Coherent Reconstruction
• IC Visibility in ATE Testing Using proteanTecs Deep Data Analytics and SmarTest 8
• SmarTest 8 Memory Demystified
• SmartTest 8 Uninterrupted Clock Solutions to Achieve Stable and Cost-Efficient Testing
• A Fast Continuity Test Method for High-Speed Loopback Pins with Capacitance
• Practical Implementation for Scan-over-HSIO with Suppress Hold on SmarTest 8
• Testing a BMS Device by use of a Dual Cell Meter
• Native IJTAG Implementation on V93000 for Debug of Complex SOC Designs
• On-ATE Failing Flop Identification with SmartShell

 

T2000 

• Simplify the Test Engineer’s Life with Custom Innovative Tools
• T2000 MMXH/MMXHE TMU Wavescope Library
• MIPI D-PHY Signal Generating Solution for Display Driver Testing
• Development of a Loadboard Module for a CAN-FD Functional Protocol Test on Advantest T2000 IPSE
• MMAF Module Picoampere Current Measurement: Device Evaluation on T2000 IPS and IPSE
• T2000 DUT Register Control Library Framework and Debugging Tools
• Achievements of Integrated MCU + Wi-Fi Chip Development Using T2000 RF RDK
• Introduction of Test Debug and Correlation Environment in RDK-Based Test Program
• T2000 Efficient Test Time Reduction on Automotive Devices Including Dynamic Pattern Modification

 

Hot Topics  

• A Smart, Low-Cost Solution fur Successful High-Volume Manufacturing on EXA Scale & SmarTest 8 Using PS5000 Universal Pins
• Break Through the Test Challenges for the Latest Beidou Navigation and Satellite Communication Chips
• 45 GHz High-Speed AD/DA Device Test Solution on V93000 EXA Scale Platform
• Rapid PMIC Test Program Development on SmarTest 8 TME Framework
• Introduction to Highly Efficient, High-Performance, Wide-Coverage V93000 PAC Test Solutions for Audio Power Amplifier Devices
• Test Challenges and Low-Cost Test Solutions on the V93000 for a WLCSP Mobile PMIC with Multi-Phase DCDC converters
• Best Practice for AVI64 Replacing WaveScale MX in Audio Applications on SmarTest 8
• Transpiler – A New approach to Automatically Convert C++ Code and Libraries to Java