Technical Program

Note: The titles below are from the VOICE 2025 program. VOICE 2026 paper titles and abstracts will be available soon.

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2026 Technical Tracks & Titles

Artificial Intelligence

  • Intelligent Probe Pin Defect Analysis: FastSAM-Based Image Extraction and AI-Driven Classification
  • Context is All You Need: Using Canonical Models and Multi-Agents to Bulletproof Automating Test Program Generation
  • Innovative HSIO Tx Termination Calibration Using a Supervised Machine Learning Approach
  • From NLP to ATE: Model-Free Search Optimization Using FAISS and ACS
  • Accelerating Test Method Development with GenAI: The TML Copilot Approach
  • Bridging Fragmented Expertise: An On-Premises Retrieval Platform for Test Engineers
  • Decoupling Test and Processing with ACS-RTDI: An Inline Fuse Build Case
  • Adaptive Testing Techniques for Next-Generation Datacenter and AI Processors
  • Self-Learning AI for Dynamic Power-Performance Co-Optimization on the V93000 Platform
  • Automated Machine Learning and Integration Framework for Scalable AI-Driven Test Optimization in Advantest V93000
  • Real-Time Anomaly Detection in ATE Using Deep Neural Networks on NVIDIA DGX Spark™
  • AutoML and Cloud-IoT for Scalable, Data-Driven Semiconductor Test Optimization
  • Enhancing Test Code Quality with AI: Automated Unit Test Generation for Your Test Methods By Using GitHub Copilot and Smart-CI
  • AI-Accelerated Case Study: Successfully Migrating a Large-Scale CPU Project from SmarTest 7 to SmarTest 8 with GitHub Copilot
  • Scaling LLM Intelligence in Semiconductor Test with MCP Servers and Multi-Agent Architectures
  • V93000 AI-Driven Test Program Development: Flexible Integration of Cutting-Edge Generative AI Technologies
  • AI-Driven Automation System for V93000 ATE

High Performance Digital

  • MIPI C-PHY 3-Level Signal Driver Low-Cost Solution with PS5000 on EXA Scale
  • Power of Visualization — Maximizing EXA Scale Background Profiling
  • Advanced Thermal Profiling and Protection for Large HPC Devices in SmarTest 8
  • Speeding Up SSN Tests with the Result Per-Core (RPC) Feature
  • 1000A HPC Device Compatible LB Design on EXA scale
  • Leveraging Java’s Multithreading Concept to Improve Test Program Loading Time
  • Test Time Reduction Using Interleaved Independent Testflow Executions
  • Fast Single-Shot Jitter Measurement in Production Test Using a PSMLS Card’s Digitizer
  • Advanced Scan-over-HSIO Implementation for AI HPC Devices on V93000
  • A Real Case Study on Testing Customized AI Devices Using IMR and Intra-Site Memory Sharing on SmarTest 8
  • Rapid Power Sequence Simulation and Verification Solution in SmarTest 8
  • Test Scheme for DDR Clock Driver Chip Based on Pin Scale Multilevel Serial
  • Using Interleaved Testflow Execution on Heterogeneous Dies for HPC Chips
  • Taming the Demand for Digital Instruments for Rising Pin Counts of HPC Testing Applications
  • Interleaved Test Flow for Chiplet Testing
  • Die-Level Testing, a New Test Insertion for High-Performance Digital
  • Experience and Best Practices of Using PSMLS for DRAM Interface SoC (RCD/CKD) Testing on V93000
  • Analysis of a PCIe Signal Path Between the Root Complex and the Endpoint to Support Scan Tests

Silicon Photonics

  • Double-Sided Optical Wafer Probing in Silicon Photonics
  • Wafer-Level HVM PIC Testing Using V93000-Triton Photonics Solution
  • PICs Wafer-Level Testing Using Dynamic Optical Alignment
  • HVM Photonics Testing Solution Using Die-Level Prober (DTS-650) and V93000

APAMs

  • Comprehensive Test Coverage for Automotive Application Specific Standard Products (ASSPs): A Tester-Based Approach
  • Leveraging XPS128+HV for Switch Charger Testing on EXA Scale
  • Test Solution for Automotive SBC-PMIC with Integrated DSI3 Interface
  • Best Practices of SmarTest 8 Test Library for PMIC on EXA Scale
  • Best Practice of Deploying PMUX02 in PAC Project
  • Best Practices for Migrating APBB Applications from SmarTest 7 to SmarTest 8 on V93000 EXA Scale
  • JESD204B/C High-Speed Protocol Solution with Pin Scale Multilevel Serial
  • An Important Research for High-Speed and High-Performance ADC HVM on the V93000 Platform

T2000

  • T2000 Utility Tools and Libraries for Faster and More Efficient Test Program Development
  • New BOST Solution for High-Speed Interface Testing in Next-Generation Display Driver ICs
  • Noise Effects in Low Voltage, High Dynamic Range Devices and Test System Design
  • PMIC 3-Minute PGM Setup on T2000: One-Click APG Boosts Throughput
  • A New Approach to Real-Time Large-Volume Data Transfer in Semiconductor Test Systems
  • A Novel Test Method for High-Efficiency, High-Volume Measurement of Basic Electrical Characteristics of MEMS Using the T2000

RF

  • An Overview of Next-Generation UWB (IEEE 802.15.4ab): Applications and Test Challenges
  • Accurate and Efficient RF PA Digital Predistortion Calibration Using WSRF-8 Measurement
  • A High-Efficiency ATE Solution for Multi-Mode Satellite Terminal SoC Chips on V93000
  • Testing RF Devices with 14Gbps High-Speed Interface Using WSRF8 and PSMSL
  • Automated RF Power De-embedding via Handler-Based Site-by-Site Calibration for SoC Mass Testing
  • WSRF20ex Migration, Featuring Wi-Fi 7 Device and Test Time Reduction Through Site-Interlacing
  • 20G High-Speed ADDA Device Testing from WSRF8 to WSRF20ex
  • Best Practice of UWB Production Testing on V93000
  • Extending RF Measurement Performance with Dual Measurement Capability in WSRF20ex
  • Best Practice of Bluetooth Channel Sounding Test on V93000
  • A New Practical Solution to Improve the Phase Noise Performance of the Measure Receiver with WSRF20ex
  • Digital Pre-Distortion with WSRF-20

Test Methodologies

  • Streamlined Read Patterns for Efficient Memory Use and Precise Failure Logging with SmarTest 8
  • Accelerating SoC Validation: From Rapid Bring-Up to Power-Performance Characterization
  • Ensuring Integrity in OTP Programming During Production Testing
  • New Streaming Scan Network API-Based Library in SmarTest 8
  • Enhancing Test Quality in SmarTest 8 Through Assertion-Centric Unit Frameworks
  • Comprehensive eFuse Burning Process Integrated Solution Based on ATE
  • Custom SmarTest 8 SmarTest Work Center Eclipse Plug-In Development Using the Device Debug API
  • HSIO Calibration and DC Measurement: Driving Accuracy for Reliable Test Solutions
  • Debugging Devices Under Test at Firmware Level with OpenOCD and PinScale 5000 Protocol Link
  • Efficient On-Die Current Meter Calibration Leveraging XPS and Adaptive Testing
  • TPAT – A Unified Temporal-Contract Framework for Deterministic Mixed-Signal Execution on the Advantest V93000
  • Effective Scan Failure Analysis Utilizing SSN Pattern Isolation TestMethod Using SmarTest 8
  • Dynamic In-Memory Test Pattern Modification Techniques for Efficient Test on High-Security Devices
  • Cost-Efficient Reliability in Wafer-Level Testing: A Novel CRES-Based Approach to Prevent Pin Degradation and Burn in Ganged XPS
  • An Efficient Algorithm for Time Measurement Unit (TMU) Data Filtering in Multisite Testing
  • Enhanced Characteristic Test Solutions Based on New AI and SmarTest 8 Features
  • Introducing Synchronized Execution – Enabling Safe Global Variable Usage in Background Thread with releaseTester() in SmarTest 8
  • AI-Assisted Offline Verification Solution for Reliable SmarTest 8 Test Programs
  • Left-Shift First Silicon Bring-up: Emulated Validation of Structural Tests Over High-Speed IO
  • ATE Machine Learning Optimized Vmin Search
  • Dedicated PS-Level Skew Testing Solution for Clock Conditioner Devices on V93000
  • Reducing Binding Time by Pattern Structure Optimization on the SmarTest 8
  • Dynamic Debug Tool
  • A Scalable Multi-Die Test Solution for Large-Scale AI Chip Production
  • SSN and IJTAG-Aware ATE: New Features in SmarTest and Tessent Shell for Efficient SSN and IJTAG Integration

Hardware and Software Design Integration

  • Enhancing Test Program Performance by Leveraging Device Setup Metrics
  • Digital Thermal Control Loop – Integrating Thermal Sensors, Protocol Link and ATCs/Handlers
  • Innovative Test Hardware Design Strategies for the V93000’s DUO Interface
  • An Integrated Solution for V93000 Test Program Quality Check and Analysis

Hot Topics

  • New DC Profiling Methodology for Optimized Performance
  • Preventing Thermal Runaway with Advanced Monitoring Solutions

Factory Automation

  • ACS Data Feed Forward (DFF): A Unified Platform for Semiconductor Test Data Collection and Distributions
  • JSON Parser Tool for Automation of Offline Result Emulation (ORE) in SmarTest 8